CCTAG: Configurable and Combinable Tagged Architecture

CCTAG: Configurable and Combinable Tagged Architecture

Speakers: Zhanpeng Liu, Master Student, Peking University

Conference: NDSS Symposium

YouTube: https://www.youtube.com/watch?v=8n6GtBcQ75k

Overview

Memory safety vulnerabilities remain a critical and pervasive threat in modern software systems, often leading to severe security breaches. Despite ongoing efforts to identify and patch these flaws, the sheer volume and complexity of codebases mean that many vulnerabilities remain undiscovered or unaddressed in a timely manner. This challenge underscores the pressing need for robust defensive mechanisms capable of mitigating both known and unknown memory-related exploits. Zhanpeng Liu's talk introduces CCTAG (Configurable and Combinable Tagged Architecture), a novel hardware/software co-design approach that aims to enhance memory safety by attaching fine-grain security metadata, or "tags," to registers and memory.

CCTAG distinguishes itself by offering unparalleled configurability and combinability, allowing diverse security policies to coexist and operate without conflicts. This approach addresses a fundamental limitation of many existing memory safety solutions, which often provide only limited protection scope or incur prohibitive performance penalties when multiple defenses are stacked. By leveraging hardware acceleration for critical security operations, CCTAG strives to overcome the traditional trade-off between strong security guarantees, acceptable performance overhead, and system compatibility, presenting a practical and efficient solution for real-world deployment.

The architecture's core innovation lies in its ability to support a wide array of tag verification and modification rules that can be configured to build various memory safety policies, from fine-grain permissions to information flow tracking. More importantly, CCTAG's policy-centric mask design enables these policies to be combined effectively, offering a layered and comprehensive defense against sophisticated memory exploitation techniques. This talk details CCTAG's design, its prototype implementation on an FPGA-based RISC-V platform, and its impressive performance characteristics when applied to real-world security applications.

Background

▶ Watch: Introduction, memory safety vulnerabilities, and defense challenges (0:00)

The landscape of software security is continually plagued by memory safety vulnerabilities, such as out-of-bounds accesses and use-after-free errors, which serve as common initial exploitation vectors for attackers. These vulnerabilities, as highlighted by security experts, are notoriously difficult to fully eliminate through software patching alone. The "Eternal War in Memory" model illustrates a typical attack progression: exploitation begins with an invalid pointer, leading to arbitrary read/write primitives, and eventually escalating to full system compromise. While various mitigation techniques exist for each step – enforcing spatial or temporal memory safety, protecting sensitive data integrity – their individual application often provides only a partial defense.

The presenter argues for the necessity of combining these defenses through both horizontal integration (broad protection across attack types) and vertical integration (layered defenses where subsequent layers catch attacks missed by preceding ones). However, simply stacking software-only defenses typically results in unacceptable performance overheads and compatibility issues. This limitation has spurred a growing interest in hardware-software co-design approaches, where critical security operations are offloaded and accelerated by specialized hardware. This trend, embraced by both industry and academia, seeks to provide robust security guarantees without compromising system efficiency.

Previous work in hardware-assisted memory safety, such as CHERI and PUMP, has demonstrated the potential of tagged architectures. These systems attach metadata to memory pointers to enforce capabilities or track memory regions. While effective, they often face challenges related to complexity, performance overhead, or limited flexibility in combining different security policies. CCTAG emerges from this context, aiming to provide a more versatile, configurable, and combinable tagged architecture that can support a diverse set of memory safety policies while maintaining a low hardware and performance footprint, thereby achieving a more practical solution for widespread adoption.

Key Findings

▶ Watch: Explaining CC Tag's configurable rules for diverse defenses (3:20)

CCTAG introduces a novel tag architecture that attaches fine-grain security metadata (tags) to both registers and memory. This foundational capability allows for the enforcement of a broad spectrum of memory safety policies, moving beyond the limitations of single-purpose defenses. A central finding is CCTAG's ability to achieve both configurability and combinability of these policies, a significant advancement over many existing hardware-assisted security mechanisms.

The architecture supports a diverse set of tag verification and modification rules, which can be dynamically configured to implement various security policies such as fine-grain permissions, memory coloring, data integrity checks, and information flow tracking. Crucially, CCTAG’s innovative policy-centric mask design enables multiple, distinct security policies to coexist and operate concurrently without conflicts. This is achieved by allowing each policy to specify a subset of tag bits within a cache line and apply policies selectively at the memory page level.

In terms of performance and overhead, CCTAG demonstrates remarkable efficiency. A prototype implementation based on the Rocket Core (a RISC-V ISA) on an FPGA shows a minimal hardware overhead of approximately 8%. This figure is significantly lower when compared to other advanced tagged architectures like CHERI and PUMP, highlighting CCTAG's cost-effectiveness. Furthermore, extensive performance evaluations using the SPEC CPU2006 benchmark suite with integrated protections (including return address, code pointer, v-table pointer integrity, and memory coloring) revealed a geometric mean overhead of only 6.68%. With a lighter cache configuration, this overhead further dropped to an impressive 4.8%, again outperforming PUMP and CHERI in terms of efficiency for combined defenses. Testing on SPEC CPU2017 yielded a geometric mean overhead of around 8%. These results underscore CCTAG's practicality for real-world applications, offering robust security with minimal performance impact.

Technical Deep Dive

▶ Watch: Prototype implementation and minimal hardware overhead (6:00)

CCTAG's technical foundation rests on a tag architecture where each 64-byte memory granular unit is associated with a 16-bit security tag. These tags are not monolithic; they can be finely controlled and combined, providing unprecedented flexibility.

Configurability is achieved through a set of fundamental tag manipulation rules:

• Tag Verification: Checking if a tag matches a specific value during memory access. This can enforce permissions or validate data states.
• Tag Modification: Setting or clearing specific tag bits upon memory writes, allowing dynamic state changes.
• Tag Propagation: Transferring tags between registers and memory, ensuring security context is maintained across data movements.

These seemingly simple primitives enable the construction of sophisticated defense mechanisms. For instance, fine-grain permissions can be implemented by assigning tags that dictate read/write/execute rights to specific memory regions. Memory coloring uses tags to differentiate memory allocations (e.g., stack vs. heap) to prevent cross-region attacks. Data integrity can be enforced by tagging sensitive data, and information flow tracking or taint analysis can use tags to trace the origin and propagation of untrusted data. CCTAG also allows for control over tagging granularity. For example, a 16-bit tag space for a 64-byte data block can be split, dedicating, say, 8 bits to secure the first 32 bytes, or allocating bits to different segments as needed, meeting diverse security requirements.

The true power of CCTAG lies in its combinability, facilitated by a policy-centric mask design. Rather than configuring each tag bit individually, policies are defined abstractly:

1. Policy Mask: Each policy specifies a subset of the available tag bits within a cache line that it cares about. For example, Policy 0 might use "odd" tag bits, while Policy 2 uses "even" tag bits.
2. Granularity: Policies can operate at different data granularities.
3. Rules: Each policy defines its specific checking and updating rules for its designated tag bits.

Crucially, CCTAG allows different policies to be applied selectively to different memory pages. For example, Policy 0 might apply to the heap, Policy 1 to the stack, and Policy 2 to all data pages. As long as policies use disjoint sets of tag bits (via their policy masks) or apply to non-overlapping memory regions, they can coexist without interference.

The hardware mechanism for combining policies is sophisticated yet efficient. When a memory access occurs, the hardware first computes an access mask based on the access granularity (e.g., if accessing 8 bytes within a 64-byte block, only specific tag bits corresponding to those 8 bytes are relevant). This access mask is then combined with the policy mask (using a bitwise AND operation) to yield a final mask that specifies the exact tag bits relevant to the current memory access and the active policy. The checking and updating values from different policies are then masked and processed together by the hardware. This ensures that only the relevant tag bits for the active policies and the specific memory access are considered, preventing conflicts and maximizing efficiency.

The prototype implementation of CCTAG is built on Rocket Core, a popular open-source RISC-V ISA processor. The hardware extensions include an extended dcache to store the 16-bit tags alongside each 64-byte cache line data. These tags are backed by a dedicated t-cache and a portion of main memory, ensuring tag persistence and efficient lookup. The system currently supports four distinct policies concurrently. Configuration of these policies is dynamic and flexible: CCTAG leverages ASR registers (Architecture State Registers) within the RISC-V architecture, which are writable in kernel mode. This allows policies to be configured via system calls, enabling the operating system to manage and apply specific security policies to user-mode applications at runtime. The speaker also noted that CCTAG's P-ratio (protection ratio) is similar to ARM MTE (Memory Tagging Extension), and it aims to be more versatile, handling unexpected behavior by raising exceptions for software to manage, akin to MTE's approach.

Demo / Proof of Concept

▶ Watch: Real-world example: Return Address Protection with LLVM (7:15)

The talk presented a compelling demonstration of CCTAG's capabilities by porting and evaluating several real-world security applications. A simple yet illustrative example was return address protection. To implement this, the LLVM compiler was modified to insert specific tag manipulation instructions. In the function prologue, after the return address is stored on the stack, an instruction like MTSD (Memory Tag Set Double Word) is issued. This instruction sets a specific tag on the saved return address, effectively marking it as inaccessible to unauthorized memory accesses. Prior to the function's return, an MTSC (Memory Tag Clear) instruction clears this tag, allowing the legitimate return instruction to read the address and execute correctly. The speaker highlighted the minimal effort required for this defense, noting that it involved adding less than 100 lines of code to LLVM.

Beyond return address protection, CCTAG was successfully applied to implement and verify several other critical defenses:

• Function pointer and v-table pointer integrity: Protecting against control-flow hijacking attacks by ensuring that function pointers and virtual table pointers are not illicitly modified.
• Heap memory coloring: Differentiating heap allocations to prevent confusion attacks where an attacker might reuse freed memory for a different object type.
• Dangling pointer sweeping: A mechanism to detect and mitigate use-after-free vulnerabilities.

These applications were verified with what the speaker referred to as "real-world security applications," demonstrating CCTAG's practical applicability.

The performance overhead of these integrated defenses was rigorously evaluated using standard benchmark suites. For SPEC CPU2006, with return address protection, code pointer integrity, v-table pointer integrity, and memory coloring all active, CCTAG exhibited a geometric mean overhead of approximately 6.68%. This integrated overhead was notably lower than the sum of individual overheads, a significant advantage attributed to the shared memory traffic overhead across multiple protection policies. Furthermore, with a "lighter cache" configuration, the overhead dropped even further to 4.8%, a figure that is lower than that observed for both PUMP and CHERI. Performance on SPEC CPU2017 also showed a respectable geometric mean overhead of around 8%. These results solidify CCTAG's claim as an efficient and practical solution for comprehensive memory safety in real-world scenarios.

Defensive Implications

▶ Watch: Summary of CCTAG's power, practicality, and efficiency (10:00)

CCTAG offers a transformative approach for defenders seeking to fortify systems against memory safety exploits. Its core strength lies in providing a robust, efficient, and highly versatile hardware-assisted mechanism for enforcing a broad spectrum of memory safety policies. This moves beyond the limitations of single-point solutions, enabling the creation of truly layered defenses. Defenders can combine spatial memory safety (preventing out-of-bounds access), temporal memory safety (mitigating use-after-free), and data integrity checks, all operating concurrently with minimal performance penalty.

The configurability of CCTAG allows security architects to tailor defenses precisely to the needs of specific applications or threat models. Instead of a one-size-fits-all approach, organizations can define custom tag verification and modification rules, allocate tag bits strategically, and apply policies at granular levels, such as per-page or per-thread. This fine-grained control is crucial for protecting highly sensitive components while minimizing impact on less critical areas.

The policy-centric mask design is a game-changer for defensive strategies. It means that multiple security concerns – for example, protecting return addresses, verifying function pointers, and enforcing heap isolation – can all be addressed simultaneously without the policies conflicting or significantly accumulating performance overhead. This horizontal and vertical integration capability provides a more comprehensive and resilient security posture, making it significantly harder for attackers to bypass multiple independent layers of defense.

Furthermore, the demonstrated low hardware overhead (8% on FPGA) and performance overhead (as low as 4.8% for integrated protections) make CCTAG a highly practical solution for real-world deployment. This efficiency addresses a major barrier that has historically prevented the widespread adoption of comprehensive memory safety solutions. For organizations considering hardware-assisted security, CCTAG presents a cost-effective and powerful alternative to existing, often more resource-intensive, tagged architectures.

However, implementing CCTAG-based defenses requires a shift in the development ecosystem. The need for compiler modifications (e.g., LLVM) to generate tag manipulation instructions implies that defenders will need updated toolchains. The ability to configure policies dynamically via ASR registers and system calls also means that operating systems or hypervisors would play a crucial role in managing and deploying these security policies, requiring kernel-level integration and control. This places a responsibility on system administrators and developers to understand and leverage these capabilities effectively to maximize the defensive benefits.

Key Takeaways

• Hardware/Software Co-design for Memory Safety: CCTAG is a novel architecture that uses a hardware-software co-design to attach fine-grain security tags to registers and memory, providing robust memory safety guarantees.
• Configurability and Combinability: It offers unparalleled configurability of tag rules and combinability of diverse security policies through a policy-centric mask design, allowing multiple defenses to coexist without conflicts.
• Low Overhead and High Efficiency: The prototype on a RISC-V FPGA demonstrates a minimal hardware overhead of 8% and impressive performance, with a geometric mean overhead of 6.68% for integrated protections on SPEC CPU2006 (dropping to 4.8% with a lighter cache).
• Versatile Defense Applications: CCTAG successfully supports a wide range of memory safety policies, including return address protection, function pointer integrity, heap memory coloring, and dangling pointer sweeping, with minimal compiler modifications (e.g., <100 lines for return address protection in LLVM).
• Practical and Cost-Effective: Compared to existing tagged architectures like CHERI and PUMP, CCTAG is shown to be more cost-effective, compatible, and efficient, making it a highly practical solution for real-world memory safety challenges.
• Dynamic Policy Management: Policies can be configured dynamically at runtime via ASR registers and system calls, providing kernel-level control over user-mode application security.

About the Speaker(s)

Zhanpeng Liu is a Master student from Peking University. His research focuses on developing hardware-software co-design solutions for enhanced system security, particularly in the domain of memory safety. This presentation on CCTAG highlights his contributions to creating practical and efficient architectures for mitigating prevalent memory vulnerabilities.